This error can occur in Stratix® V, Arria® V, and Cyclone® V devices when the PLL Intel® FPGA IP is sourced by a global or regional network where that network is driven by a dedicated clock input pin. The connection of a dedicated clock pin to a phase-locked loop (PLL) over a global / regional network is legal, however, the Quartus® II software will not allow this connection without an explicit promotion of the clock to the global or regional resource through a clock control block.
Insert an ALTCLKCTRL Intel® FPGA IP in the clock path between the dedicated clock input pin and the PLL Intel FPGA IP. Note, using a global primitive or global signal assignment for the clock signal is not sufficient, the ALTCLKCTRL Intel® FPGA IP must be instantiated in your design.
This is not necessary when the clock input pin has dedicated access to the PLL Intel FPGA IP.