Article ID: 000082557 Content Type: Troubleshooting Last Reviewed: 10/01/2013

Stratix V Pin Connection Guidelines: Known Issues

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Issue 155552: Version 1.6

In the Pin Connection Guidelines it states "If you are using a -1 or -2 core speed grade, you must connect the core VCC to 0.9V" but this is only partially correct and will be updated to state "If you are using a -1 or -2 core speed grade, you must connect the core VCC to 0.9V, if you are using a -2L core speed grade, you must connect the core VCC to 0.85V".

Issue 80577: Version 1.4

Pin Connection Guidelines versions 1.4 and previous omitted that if any PLL is utilized the RREF precision calibration resistors are needed.  This is independent of the utilization of any transceiver channels or dedicated REFCLK I/O.

Issue 63751: Version 1.3

DCLK is not listed as a dual purpose pin.  DCLK can be configured to be a user I/O pin after configuration when the configuration mode is an Active mode.

Issue 34856: Version 1.2

There is an error with VCCIO, VCCPGM, and VCCPD.

Page 12, 14, 16, and 18 it states: "VCCPD must be greater than or equal to VCCPGM." which is incorrect.

The Stratix V Pin Connection Guidelines will be corrected to state: "VCCPD must be greater than or equal to VCCIO."

Resolution

Resolved issues:

Issue 376579: Version 1.1

The CLK[1:27]p/n Name, Pin Type, Pin Description, and Connection Guidelines are incorrect, these clock pins have dual purpose functionality and are capable of being used as output pins.  Here are the corrections which will appear in a future version of this document:

Pin Name: CLK[0:27]p/n

Pin Type: I/O, Clock Input

Pin Description: Dedicated high speed clock input pins that can also be used for data inputs/outputs. Differential input OCT Rd, single ended input OCT Rt and single ended output OCT Rs are supported on these pins.

Connection Guidelines: Unused pins can be tied to GND or left unconnected. If unconnected, use the Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull up resistor enabled, or as outputs driving GND.

Issue 369370, Version 1.1

The Stratix® V Pin Connection Guidelines provide the incorrect information for PORSEL. In Stratix V devices there is no PORSEL pin and selection of the POR is taken into account by the MSEL pin settings. For more information on the POR delay setting refer to Table 9-4 of Chapter 9. Configuration, Design Security, and Remote System Upgrades in Stratix V Devices (PDF). 

Issue 367942, Version 1.1

The Stratix® V Pin Connection Guidelines provide the incorrect information for VCC, VCCHIP_[L,R] and VCCHSSI_[L,R] regarding power supply sharing requirements, and connection for the RZQ_[#] pins when using calibrated on chip termination [OCT].

When using VCCHIP_[L,R] and VCCHSSI_[L,R], they must share the same regulator as VCC. Version 1.1 of the PCG incorrectly says they "may" share the same supply in the following locations:

  • Connection Guidelines for VCC (page 9)
  • Connection Guidelines for VCCHIP_[L,R] (page 11)
  • Connection Guidelines for VCCHSSI_[L,R] (page 11)
  • Notes for VCC, VCCHIP_[L,R] and VCCHSSI_[L,R] (page 14)

Also, in all of these cases, the sentence stating "However if VCCHIP, VCCHSSI and VCC do not share the same supply, then VCC must be fully ramped up before VCCHIP and VCCHSSI are power on" will be removed.

The connection guidelines for RZQ_[#] on page 9 incorrectly state "When using OCT tie these pins to the required banks VCCIO through either a 240 ohm or 100 ohm resistor, depending on the desired OCT impedance."

The connection guidelines for RZQ_[#] should state "When using OCT tie these pins to GND through either a 240 ohm or 100 ohm resistor, depending on the desired OCT impedance."

Related Products

This article applies to 2 products

Stratix® V E FPGA
Stratix® V GX FPGA

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