Article ID: 000082535 Content Type: Troubleshooting Last Reviewed: 08/14/2018

Why are the message data allocated vectors (0x05c) in the Intel® Arria® 10 PCIe* MSI capability structure are not writable when multiple message enable is set?


  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express

    Critical Issue


    All bits of Message Data field in PCIe* configuration space MSI capability structure should be always readable and writable by software. The value written into the Message Data field from the CRA interface should be identical to the value read out later from CRA interface.

    When multiple message enable is enabled, the MSI packet is formed using the allocated vector bits from the user interrupt, and the MSB of the data field are from the Message Data field in configuration space MSI capability structure.

    Due to a problem with the Intel® Arria® 10 PCIe*, the Message Data allocated vector bits are not writable when multiple message enable bit is set.

    For example, when multiple message enable is set to 010, 32'hFFFFFFFF are written into configuration space Message Data field and user interrupt inputs are all 0, then software can only read 32'hFFFFFFFC.

    This is a minor bug since the MSI packet generated by the Intel® Arria® 10 PCIe* IP is still correct.


    No workaround for this problem exists. The user application and software should be aware of the limitation and be aware that the message data allocated vector bits are not writable by software when multiple message enable is set.

    This problem will not be fixed in a future release of the Intel® Quartus® Prime software.



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