Article ID: 000082526 Content Type: Troubleshooting Last Reviewed: 08/20/2018

Why does the Intel® Arria® 10 PCIe* Hard IP Root Port not update AER registers when receiving a malformed completion packet?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    When the Intel® Arria® 10 PCIe* Hard IP is configured as a Root Port if it sends a memory read request to the endpoint, and the endpoint returns a malformed completion packet, the root port may not update the AER register and silently drop it.

     

    This problem has been confirmed as a silicon bug.

    Resolution

    To work around this problem, the user application needs to be aware of this limitation and implement a timer for non-posted TLPs sent while waiting for completion packets. User logic then needs to verify the length field value matches the actual packet length for completion packets sent by end points.

    This problem is not scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

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