Article ID: 000082190 Content Type: Troubleshooting Last Reviewed: 09/26/2022

Why is the PCI Express to DDR2 for Arria® II GX reference design given by Intel not compiling successfully?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The following error might appear during the fitter stage when compiling the PCIe to DDR2 for Arria® II GX reference design:

Error (176623): The source driving the following ports must be the same

Error (176624): Source top_example_chaining_pipen1b_ddr:core|ddr2_sodimm_x64:ddr2_sodimm_x64_inst|ddr2_sodimm_x64_controller_phy:ddr2_sodimm_x64_controller_phy_inst|ddr2_sodimm_x64_phy:ddr2_sodimm_x64_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy:ddr2_sodimm_x64_phy_alt_mem_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy_seq_wrapper:seq_wrapper|ddr2_sodimm_x64_phy_alt_mem_phy_seq:seq_inst|seq_mem_clk_disable drives port SRESET on atom top_example_chaining_pipen1b_ddr:core|ddr2_sodimm_x64:ddr2_sodimm_x64_inst|ddr2_sodimm_x64_controller_phy:ddr2_sodimm_x64_controller_phy_inst|ddr2_sodimm_x64_phy:ddr2_sodimm_x64_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy:ddr2_sodimm_x64_phy_alt_mem_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].mem_clk_ddio

Error (176624): Source GND drives port SRESET on atom top_example_chaining_pipen1b_ddr:core|ddr2_sodimm_x64:ddr2_sodimm_x64_inst|ddr2_sodimm_x64_controller_phy:ddr2_sodimm_x64_controller_phy_inst|ddr2_sodimm_x64_phy:ddr2_sodimm_x64_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy:ddr2_sodimm_x64_phy_alt_mem_phy_inst|ddr2_sodimm_x64_phy_alt_mem_phy_clk_reset:clk|ddio_mimic

This issue exists in Intel® Quartus® software and IP version 10.1 and above.

Resolution

To resolve the error, you need to modify file ddr2_sodium_x64_phy_alt_mem_phy.v

Find "sreset" signal in module arriaii_ddio_in instantiation:

Change:

arriaii_ddio_in ddio_mimic(
    .datain     (fb_clk),
    .clk        (measure_clk_2x),
    .clkn       (),
    // synopsys translate_off
    .devclrn(),
    .devpor(),
   // synopsys translate_on
    .ena        (1\'b1),
    .areset     (1\'b0),
    .sreset     (1\'b0),
    .regoutlo   (),
    .regouthi   (mimic_data_2x),
    .dfflo      ()
);

To

arriaii_ddio_in ddio_mimic(
    .datain     (fb_clk),
    .clk        (measure_clk_2x),
    .clkn       (),
    // synopsys translate_off
    .devclrn(),
    .devpor(),
   // synopsys translate_on
    .ena        (1\'b1),
    .areset     (1\'b0),
    .sreset     (seq_clk_disable || ctrl_clk_disable[1]),
    .regoutlo   (),
    .regouthi   (mimic_data_2x),
    .dfflo      ()
);

Related Products

This article applies to 1 products

Arria® II GX FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.