Why do the carry look-ahead adder and ripple-carry adder from the Altera Example Web Site run at the same speed when implemented in the MAX PLUS II software?

Description When you implement the two different adders under the default conditions, they function at the same speed. This is because during the default conditions, parallel expanders/carry chains (depending on the device you are targeting) are ignored and not used in the compilation of the design. The carry look-ahead adder is faster because it makes use of the carry signal from each full-bit adder to calculate a total sum at a faster speed. To have this function implemented in the adder, you need to use the "fast synthesis" style.

To change to Fast Synthesis style, go to the Assign menu on the MAX PLUS II software and select Global Project Logic Synthesis. Next, click on "Define Synthesis Style". Note that under the "Normal" style, Parallel Expanders/Carry Chains are off. However, if you change the Style to "Fast" from the pull-down menu, Parallel Expanders/Carry Chains will be turned on.

Once this "Fast" style is turned on and you recompile your design, the carry-look-ahead adder will be implemented with Parallel Expanders/Carry Chains to speed up the calculation. If you do the same thing to the ripple-carry adder, it will still speed up the adder because the entire design will be synthesized with a faster style. However, the method that is used to calculate the sum will still be slower than the carry-look-ahead adder. If you look at the report file for each adder, you will note that with the fast synthesis style, the carry-look adder uses more Parallel Expanders/Carry Chains.