DisplayPort Audio Feature in HBR2 Data Rate Requires 4 Symbols per Clock

When the DisplayPort Audio feature is enabled with MAX_LINK_RATE = HBR2 amd SYMBOLS_PER_CLOCK = 2 your DisplayPort design fails to meet timing in the Quartus Prime software. The design fails to meet timing with the link speed clock at 270 MHz. This issue does not affect designs at HBR data rate with 2 symbols per clock.

To work around this issue, use 4 symbols per clock when you enable the audio feature at HBR2 data rate.

This issue will be fixed in a future version of the DisplayPort IP core.