Article ID: 000081971 Content Type: Troubleshooting Last Reviewed: 10/17/2014

Incorrect TrustZone Information in SoC Technical Reference Manual

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

The Arria V Device Handbook and Arria V Device Handbook contain incorrect information about the TrustZone security level for the transactions initiated by the Ethernet MAC and ETR master interfaces. The Interconnect chapter of Volume 3: Hard Processor System Technical Reference Manual in these handbooks incorrectly indicates that these transactions are nonsecure.

Resolution

The following table lists the correct TrustZone security levels for transactions from these component’s masters.

Interconnect Master Interface
MastersTrustZone Security
EMAC 0/1Secure
ETRPer Transaction

Related Products

This article applies to 2 products

Arria® V FPGAs and SoC FPGAs
Cyclone® V FPGAs and SoC FPGAs

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