Article ID: 000081962 Content Type: Troubleshooting Last Reviewed: 07/15/2014

Why do I see timing problems reported when using derive_pll_clocks using UniPHY-based memory controllers?

Environment

  • Quartus® II Subscription Edition
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    Description

    Due to a problem in the Quartus® II software version 13.0 SP1 with patch 1.dp5, you will observe certain warning messages during the Fitter stage of compilation as well as Report DDR issues within TimeQuest timing analyzer when the following criteria are met:

    • derive_pll_clocks is called in a Synopsys Design Constraint (.sdc) file after the .sdc files generated with the UniPHY-based megafunction
    • UniPHY-based DDR2 or DDR3 memory contoller used with the following frequency ranges:

    Device

    Memory Frequency (MHz)

    Cyclone® V E/GX/GT

    250 <= f <= 400

    Arria® V GX/GT

    250 <= f < 450

    The following warning may appear during static timing analysis using TimeQuest timing analyzer:

    Warning (332088): No paths exist between clock target "<variation name>|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk" of clock "<variation name>|altera_pll_i|general[0].gpll_afi_clk" and its clock source. Assuming zero source clock latency.
    Resolution

    To work around this issue, download and install the patch below. The Quartus II software version 13.0 SP1 patch 1.dp5 must be installed for the patch below to function properly.

    The EMIF IP must be regenerated and the design re-compiled after the patch above is successfully installed.

    This issue will be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 5 products

    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA

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