Description
In an ARM-based system, two levels of interrupt are available: fast interrupt request (FIQ) for fast, low-latency interrupt handling, and interrupt request (IRQ) for general interrupts.
An ARM processor handles an exception (a branch instruction) by loading an instruction from a specific address defined by the exception. An IRQ exception's first instruction is fetched from address 4.All instructions in the exception handler table must be branch instructions, except for the last one. The last exception in the table is the FIQ. Since nothing follows this handler, the first instruction can be a useful instruction (i.e., not a branch instruction).
The interrupt latency is also reduced for FIQ interrupts because the extra banked registers may be used to maximum efficiency by preventing the need for a context save.