Critical Issue
Description
With the variable decoder, when the Number of check
symbols and Symbols per codeword values are
similar, for example, 5 and 6, respectively, the Avalon-ST interface
on the source side fails and the sop and eop overlap.
This issue affects all Verilog HDL variable decoder designs.
The design fails simulation.
Resolution
To avoid this issue, create a VHDL design model and use the VHDL testbench.
This issue will be fixed in a future version of the Reed-Solomon Compiler.