100G Interlaken IP Core User Guide Specifies Wrong Bits in ALIGN Register

The 100G Interlaken MegaCore Function User Guide describes the ALIGN register at offset 0x20 as follows:

• Bit 1: TX lanes are aligned.
• Bit 0: RX lanes are aligned.

However, the TX lane alignment field is actually in bit 12 of the register.

The correct register description is:

• Bit 12: TX lanes are aligned.
• Bit 0: RX lanes are aligned.

This issue is present in the 100G Interlaken MegaCore Function User Guides v12.1 and v12.1 SP1.

You should ignore all other bits of this register. Some of them do not read as regular Reserved bits, with the read value of 0. However, bits [11:1] and bits [31:13] of the ALIGN register should be ignored.

To work around this issue, read TX lane alignment status from bit 12 of the ALIGN register and ignore the values in all bits except bits 0 and 12.

This issue is fixed in version 13.0 of the 100G Interlaken MegaCore Function User Guide (dated 05.06.2013).