Article ID: 000081312 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What are the Vih and Vil levels for the input buffers of the Stratix® and Stratix® GX configuration dual-purpose pins, such as the DATA[7..0] and PPA pins (nWS, nRS, CS and nCS) during configuration?

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Description The Vih and Vil levels for the input buffers of the Stratix and Stratix GX configuration dual-purpose pins depend on the VCCIO of the IO bank where these dual-purpose pins reside.

For an example, if the VCCIO of the IO bank of the DATA0 pin is 3.3V, then the corresponding Vih and Vil levels of the DATA0 input buffer are similar with a 3.3V LVTTL input buffer. The same applies for other VCCIO values, as well. Assume that the IO bank of the DATA0 pin is 1.5V, then the DATA0 input buffer has similar Vih and Vil levels with a 1.5V LVTTL input buffer.

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Stratix® FPGAs

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