Due to a problem in the SoC EDS software version 15.0.1 and earlier, this error may be seen when compiling a Software Preloader (SPL) targeting Cyclone® V SOC or Arria® V SOC for designs with HPS SDRAM ECC enabled in Qsys.
From 15.0.1 the BSP setting SDRAM_SCRUB_REMAIN_REGION is enabled by default, but SDRAM_SCRUBBING is disabled by default causing a conflict
To work around this problem:
- Enable SDRAM_SCRUBBING for your SPL BSP in the advanced section of the BSP-Editor GUI
1. Re-generate the BSP
2. Re-compile the SPL: Run make clean and make in your generated SPL directory
See the SoC EDS User guide for more detail on SDRAM_SCRUB_REMAIN_REGION and SDRAM_SCRUBBING
This problem is scheduled to be fixed in a future version of the SoC EDS software.