Article ID: 000081278 Content Type: Troubleshooting Last Reviewed: 03/18/2016

sdram.c:40:4: error: #error If ECC is enabled, Scrubbing should also be enabled.

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the SoC EDS software version 15.0.1 and earlier, this error may be seen when compiling a Software Preloader (SPL) targeting Cyclone® V SOC or Arria® V SOC  for designs with HPS SDRAM ECC enabled in Qsys.
    From 15.0.1 the BSP setting SDRAM_SCRUB_REMAIN_REGION  is enabled by default, but SDRAM_SCRUBBING is disabled by default causing a conflict

    Resolution

    To work around this problem:


     - Enable SDRAM_SCRUBBING for your SPL BSP in the advanced section of the BSP-Editor GUI

    Then:
     1. Re-generate the BSP
     2. Re-compile the SPL: Run make clean and make in your generated SPL directory

    See the SoC EDS User guide for more detail on SDRAM_SCRUB_REMAIN_REGION  and SDRAM_SCRUBBING

    This problem is scheduled to be fixed in a future version of the SoC EDS software.

    Related Products

    This article applies to 5 products

    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA

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