Article ID: 000081260 Content Type: Troubleshooting Last Reviewed: 09/11/2012

In ALTCLKCTRL MegaWizard, how does the register 'ena' port with 'Double register with input clock' affect the output signal?

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Description

Using \'Double register with input clock\', which added additional register, aids in asynchronous enable/disable clock and improve the meta-stability state. Figure 1 shown the implementation of register \'ena\' in Altera device.

Figure 1.

Figure 1

 

In ALTCLKCTRL MegaWizard, if user select register \'ena\' port with \'Double register with input clock\', the output clock will be available two inclk falling edge after \'ena\' toggle high. Refer to Figure 2 for the functional diagram.

Figure 2.

Figure 1

 

The output clock will stop two inclk falling edge after \'ena\' toggle low. Refer to Figure 3 for the functional diagram.

Figure 3.

Figure 1

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Stratix® IV GX FPGA

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