Why is gxb_rx_pll_locked signal of CPRI core not asserted in slave mode under simulating even though there is data in RX direction?

Please check whether gxb_pll_locked and reset_done signals are asserted. If they are all deasserted, the root cause may due to that there is no active gxb_pll_inclk clock driving into slave CPRI core. The gxb_pll_inclk is input clock to the transmitter PLL in CPRI IP core configured in slave clocking mode. The transmitter PLL could not enter locked status if there is no active gxb_pll_inclk clock; and then internal reset module could not finish reset sequence; then you may see that gxb_rx_pll_locked signal is not asserted even though there is data in RX direction.

Please provide an active clock to gxb_pll_inclk input of slave mode CPRI core.