Article ID: 000081158 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any known issues with LVPECL support for Stratix III devices in the Quartus II software versions 7.2 SP3 and earlier?

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Description

Yes, when you use LVPECL on a dedicated clock input on a row I/O bank, the Quartus® II software versions 7.2 SP3 and earlier incorrectly allow you to assign 3.0V and 3.3V I/O standards to output pins in the same bank as the LVPECL clock input. 

When you use LVPECL on a dedicated clock input pin located on a row bank in Stratix® III devices, VCCPD must be connected to 2.5V. When VCCPD is connected to 2.5V, the I/O bank can support only output operations for voltages less than or equal to 2.5V. 

This issue is scheduled to be fixed in a future release of the Quartus II software.  

Related Products

This article applies to 1 products

Stratix® III FPGAs

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