Article ID: 000081145 Content Type: Troubleshooting Last Reviewed: 08/04/2023

Can I choose the DCLK frequency for slave devices when using a multiple device Active Serial (AS) configuration scheme in 28nm devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, when using a multiple device AS configuration scheme in Stratix®  V, Arria®  V, and Cyclone®  V devices,  a 12.5 MHz clock is always used for DCLK of the slave devices, while you can choose a 12.5, 25, 50, or 100 MHz clock for the DCLK of the master device.

Resolution

When using a multiple device AS configuration scheme in Stratix®  V, Arria®  V, and Cyclone®  V devices,  a 12.5 MHz clock is always used for the DCLK of the slave devices.

Related Products

This article applies to 14 products

Cyclone® V SX SoC FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Arria® V GX FPGA
Cyclone® V GT FPGA
Arria® V GT FPGA
Arria® V GZ FPGA
Cyclone® V E FPGA
Cyclone® V GX FPGA
Arria® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA

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