Article ID: 000081003 Content Type: Troubleshooting Last Reviewed: 07/04/2016

DisplayPort Control Symbols (FS/FE) Mistakenly Inserted at Every End of Video Line

Environment

    Intel® Quartus® Prime Pro Edition
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Critical Issue

Description

The DisplayPort specification requires the last transfer unit (TU) of a horizontal video line must end with a Blanking Start (BS) symbol and must not end with a Fill Start (FS) and Fill End (FE) insertion. However, the Altera DisplayPort TX core may mistakenly insert FS and FE at every end of video line. This behavior occurs for certain combination of resolutions and color depths, when the packed data rate is very close to the link bandwidth.

The total symbols required per line per lane (TS) across color depths can be calculated as:

  • 16 bpp: TS = (active pixels per line x (4 x 1) / 2) / lane count
  • 18 bpp: TS = (active pixels per line x (4 x 9) / 16) / lane count
  • 20 bpp: TS = (active pixels per line x (4 x 5) / 8) / lane count
  • 24 bpp: TS = (active pixels per line x (4 x 3) / 4) / lane count
  • 30 bpp: TS = (active pixels per line x (4 x 15) / 16) / lane count
  • 32 bpp: TS = (active pixels per line x (4 x 2) / 2) / lane count
  • 36 bpp: TS = (active pixels per line x (4 x 9) / 8) / lane count
  • 48 bpp: TS = (active pixels per line x (4 x 3) / 3) / lane count

The DisplayPort TX core may mistakenly insert FS and FE at the end of every video line if the required total symbols (TS) are in multiple of average valid symbols per TU (avg_bytes_tu) in the following conditions:

  • When SYMBOLS_PER_CLOCK = 2 and avg_bytes_tu > 62
  • When SYMBOLS_PER_CLOCK = 4 and avg_bytes_tu > 60

This non compliance to the DisplayPort specification may cause interoperability issues with some devices.

Resolution

There is no workaround for this issue.

This issue is fixed in version 16.0 of the DisplayPort IP core.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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