Article ID: 000080989 Content Type: Troubleshooting Last Reviewed: 06/18/2014

Why does my Cyclone V Hard IP for PCI Express simulation get stuck at the L0 state when using Aldec Riviera-PRO or Aldec ActiveHDL?

Environment

  • Simulation
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Cyclone® V Hard IP for PCI Express® simulation can get stuck in the L0 state because the encrypted simulation models are attempting to use a Quartus® II define statement that is not included in the riviera_pro.tcl simulation script.

    Resolution

    Go into riviera_pro.tcl and update the following lines:

    from:
      vlog "/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver
      vlog "/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver
      vlog "/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver
      vlog "/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver

    to:
      vlog define QUARTUS "/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver
      vlog define QUARTUS "/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver
      vlog define QUARTUS "/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver
      vlog define QUARTUS "/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver

    Any line that has ncrypt needs a define QUARTUS added to it.

    Run in the Aldec tool the following commands for commands for successful simulation:

    Source riviera_pro.tcl

    ld_debug
    run

    Related Products

    This article applies to 5 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Cyclone® V GX FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SE SoC FPGA

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