Article ID: 000080866 Content Type: Troubleshooting Last Reviewed: 07/17/2019

Riviera* Simulation Errors of the Intel® Stratix® 10 Avalon®-ST and Single Root I/O Virtualization (SRIOV) Interface for PCI Express* Solutions IP.

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem wih the ALDEC* Riviera* simulation tool, the following or similar error will be seen when simulating the Intel® Stratix® 10 Avalon®-ST and Single Root I/O Virtualization (SRIOV) Interface for PCI Express* Solutions IP.

    ALOG: Error: VCP2950 SEG_WIDTH*2 is not a valid right-side of defparam.

    Resolution

    No workaround is available when using the ALDEC* Riviera* simulation tool. This problem is not seen with other supported simulators.

    This problem has been reported to ALDEC*, a fix is scheduled for a future release of the ALDEC* Riviera* simulation tool.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.