Article ID: 000080866 Content Type: Troubleshooting Last Reviewed: 11/26/2024

Riviera* Simulation Errors of the Stratix® 10 Avalon® Streaming and Single Root I/O Virtualization (SRIOV) Interface for PCI Express* Solutions IP.

Environment

    Intel® Quartus® Prime Pro Edition
    Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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Critical Issue

Description

Due to a problem wih the ALDEC* Riviera* simulation tool, the following or similar error will be seen when simulating the Stratix® 10 Avalon® Streaming and Single Root I/O Virtualization (SRIOV) Interface for PCI Express* Solutions IP.

ALOG: Error: VCP2950 SEG_WIDTH*2 is not a valid right-side of defparam.

Resolution

No workaround is available when using the ALDEC* Riviera* simulation tool. This problem is not seen with other supported simulators.

This problem has been reported to ALDEC*.

Related Products

This article applies to 5 products

Intel® Stratix® 10 GX FPGA
Intel® Stratix® 10 SX SoC FPGA
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 TX FPGA
Intel® Stratix® 10 FPGAs and SoC FPGAs

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