Article ID: 000080828 Content Type: Troubleshooting Last Reviewed: 08/18/2023

Why are the stable and resolution valid bits within the Status register of the Clocked Video Input II Intel® FPGA IP stuck at 0?

Environment

    Intel® Quartus® Prime Standard Edition
    Intel® Quartus® Prime Pro Edition
    Clocked Video Input II (4K Ready) Intel® FPGA IP
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Description

Due to a problem with the Clocked Video Input II (4K Ready) Intel® FPGA IP in Intel® Quartus® Prime Software version 17.0 software, you may observe the above problem if you are using embedded synchronization mode.

 

Resolution

There is no workaround for this problem.

Related Products

This article applies to 8 products

Cyclone® IV FPGAs
Stratix® V FPGAs
Cyclone® V FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 LP FPGA
Arria® V FPGAs and SoC FPGAs
Stratix® IV FPGAs
Arria® II FPGAs

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