Article ID: 000080799 Content Type: Error Messages Last Reviewed: 06/20/2018

Error (20181) The permit_cal input of IOPLL <downstream PLL> is not connected correctly.

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • IOPLL Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Intel® Quartus® Prime Pro Edition software version 18.0 Update 1, you may see this error message when compiling an Intel Stratix® 10 design with cascaded PLLs. This error message is new in version 18.0 Update 1 and is the result of a new legality check to prevent downstream PLLs being calibrated when the upstream PLL has failed calibration.

    Error (20181) The permit_cal input of IOPLL <downstream PLL> is not connected correctly. The permit_cal port of downstream IOPLL <downstream PLL> should be exported using the IOPLL IP Parameter Editor and connected to the locked output of upstream IOPLL <upstream PLL>

    Resolution

    To avoid this error, ensure that the downstream PLL's 'permit_cal' input port is exposed by checking 'Connect to an upstream PLL through Core Clock Network Cascading (create a permit_cal Input signal)' in the Parameter Editor GUI for the PLL and this port is connected to the locked port of the upstream PLL.

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