Article ID: 000080726 Content Type: Troubleshooting Last Reviewed: 06/18/2012

RTL Modification Required for Top/Bottom Bonding on Arria V and Cyclone V Devices

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    This problem affects DDR2 and DDR3 products.

    For Arria V and Cyclone V devices, you must modify the resulting RTL code if you want to bond a hard interface on the top of the device with one on the bottom.

    Resolution

    The workaround for this issue is as follows:

    The I/O pin pll_ref_clk cannot route to both the top and bottom PLLs; therefore it is necessary to route the I/O through the GCLK network and fanout to both PLLs.

    Add the following lines to your RTL file:

    wire global_pll_ref_clk; altclkctrl #( .clock_type("GLOBAL CLOCK"), .number_of_clocks(1) ) global_pll_ref_clk_inst ( .inclk(pll_ref_clk),.outclk(global_pll_ref_clk));

    Replace the input signal pll_ref_clk in your hmi0 and hmi1 instantiations with global_pll_ref_clk.

    This issue will be fixed in a future version.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® IV FPGAs

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