This problem affects DDR2 and DDR3 products.
For Arria V and Cyclone V devices, you must modify the resulting RTL code if you want to bond a hard interface on the top of the device with one on the bottom.
The workaround for this issue is as follows:
The I/O pin
pll_ref_clk cannot route to both
the top and bottom PLLs; therefore it is necessary to route the
I/O through the GCLK network and fanout to both PLLs.
Add the following lines to your RTL file:
altclkctrl #( .clock_type("GLOBAL CLOCK"), .number_of_clocks(1)
) global_pll_ref_clk_inst ( .inclk(pll_ref_clk),.outclk(global_pll_ref_clk));
Replace the input signal
pll_ref_clk in your
This issue will be fixed in a future version.