Article ID: 000080680 Content Type: Troubleshooting Last Reviewed: 10/23/2019

Why does my Intel® FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express* show lower read performance in Intel® Quartus® Prime Pro version 19.3?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP+ for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Intel® FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express* currently supports up to 64 outstanding requests with a Max Read request size of 512 Bytes. If the round trip latency (Time from Memory Read to Completion) is greater than 1.5 us, the number of outstanding requests may not be enough to saturate the Read throughput.

    Resolution

     

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 DX FPGA

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.