Article ID: 000080672 Content Type: Troubleshooting Last Reviewed: 06/19/2019

Why does the 25G Ethernet Intel® FPGA IP example design with "Enable 10G/25G dynamic rate switching" option enabled and "Enable RS-FEC" disabled halted unexpectedly during Mentor* ModelSim* simulation ?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the 25G Ethernet Intel® FPGA IP in Intel® Quartus® Prime Pro edition version 18.1, the example design with "Enable 10G/25G dynamic
    rate switching" option enabled and "Enable RS-FEC" option disabled may halt unexpectedly during simulation within Mentor* ModelSim* simulator.  

    The modelsim transcript will stop at the simulation stages below:
    # Switching to 25G mode : 25G Reconfig start
    # Switching to 25G mode : 25G Reconfig End
    #Waiting for RX alignment  

    Resolution

    There is no workaround for this problem.

    This problem has been fixed starting with Intel® Quartus® Prime Pro software version 19.1.

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