Why does the 25G Ethernet Intel® FPGA IP example design with "Enable 10G/25G dynamic rate switching" option enabled and "Enable RS-FEC" disabled halted unexpectedly during Mentor* ModelSim* simulation ?

Due to a problem with the 25G Ethernet Intel® FPGA IP in Intel® Quartus® Prime Pro edition version 18.1, the example design with "Enable 10G/25G dynamic
rate switching" option enabled and "Enable RS-FEC" option disabled may halt unexpectedly during simulation within Mentor* ModelSim* simulator.  

The modelsim transcript will stop at the simulation stages below:
# Switching to 25G mode : 25G Reconfig start
# Switching to 25G mode : 25G Reconfig End
#Waiting for RX alignment  

There is no workaround for this problem.

This problem has been fixed starting with Intel® Quartus® Prime Pro software version 19.1.