What is the adaptive synchronization feature support plan for the DisplayPort Intel® FPGA IP core?

Below is the Adaptive Synchronization feature support plan by Intel® Quartus® Prime Pro Edition Software and Standard Edition Software.

1. For DisplayPort Source implementation, refer to the DisplayPort Intel® FPGA user guide documentation and Video Input Feature Comparisons table to enable the adaptive synchronization feature.
2. For DisplayPort Sink implementation, refer to the Design Example Variant table and the Intel® Stratix® 10 DisplayPort SST Parallel Loopback with AdaptiveSync Support section in DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide to enable the adaptive sync feature in the DPCD register.

Refer to the table below for the DisplayPort Intel® FPGA IP core Adaptive Synchronization support plan.