Article ID: 000080661 Content Type: Error Messages Last Reviewed: 06/24/2019

Error(16186): Can't elaborate top-level user hierarchy: "VHDL info at pcie_example_design.vhd(1337): back to vhdl to continue elaboration" 

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Stratix® 10 Avalon® -ST Hard IP for PCIe* Design Example version 18.1 , you may observe this error when the "Generate HDL format" option is set to VHDL.
     

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition software version 18.1 set the "Generate HDL format" option to Verilog. This problem has been fixed beginning with  the Intel® Quartus® Prime Pro Edition software version 19.1

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