Due to a problem in the Quartus® Prime Pro Edition Software version 18.1 and earlier, you may see the HDL coded ramstyle attribute reported in the synthesis report, Processing > Compilation Report > Synthesis > Source Assignments > Ignored Source Level Assignment.
This happens when you have ramstyle attribute being written in Verilog HDL or VHDL code for your design as below.
Verilog: (* ramstyle = "M20K" *) reg [<msb>:<lsb>] <variable_name>[<msb>:<lsb>];
VHDL: attribute ramstyle : string;
attribute ramstyle of <object> : <object_class> is <string_value>;
It is safe to Ignore the report for "Ignored Source Level Assignments" for "ramstyle". RAM will still be implemented correctly in Fitter. It is shown in fitter report under Fitter -> Place Stage -> RAM Summary report.
This problem is fixed starting with the Quartus® Prime Pro Edition Software version 21.1.