Article ID: 000080539 Content Type: Error Messages Last Reviewed: 06/29/2014

Error: ATX PLL parameter 'output_clock_frequency' is set to an illegal value

Environment

  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
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Description

You may see the following error if entering a high precision (number of decimal places) transceiver refclk and datarate into a transceiver PHY MegaWizard™ on Stratix® V GX devices.

Error: ATX PLL parameter 'output_clock_frequency' is set to an illegal value

The error is due to an incorrect legality check in Quartus® II software versions 12.1sp1 and earlier.

Resolution

To work around this issue, you can reduce the precision of the refclk and datarate in the transceiver PHY MegaWizard. The Bandwidth of the transceiver Tx PLL and CDR will support your actual requirement.

This issue will be fixed in a future version of the Quartus II software.

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