Description
When you generate a Platform Designer system with the On-Chip Memory (RAM or ROM) FPGA IP and select Enable In-System Memory Content Editor feature
You may get the following warning:
Warning: The ENABLE_RUNTIME_MOD LPM_HINT is no longer used to enable the In-System Memory Content Editor. Please refer to the RAM_1PORT and ROM_1PORT IPs to generate a memory suitable for use with ISMCE.
If this warning is displayed, the ISMCE will not be instantiated in the system as expected.
Resolution
To work around this problem, the following methods can be used for debug.
- Use the System Console tool to read and write the contents of the On-Chip Memory IP. You would need to add a JTAG to Avalon Master Bridge component and connect it to the On-Chip Memory s1 port. If you are not familiar with System Console, there is a video training on YouTube. https://www.youtube.com/watch?v=oGUeqeFqOW4
- Use a processor to read and write the contents of the On-Chip Memory IP.
- Use the RAM 1-port IP. This IP doesn't have an Avalon bus, so you would have to build an adapter to connect in to a Platform Designer system.
This problem is fixed starting in version 19.4 of the Platform Designer software.