Article ID: 000080474 Content Type: Error Messages Last Reviewed: 07/16/2019

Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/cluster_greedy.c, Line: 3682

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Standard Edition software version 18.1, you may see this internal error when compiling a design that instantiates one or more Clock Control Blocks(ALTCLKCTRL). This problem occurs when targeting Cyclone® V devices. 

    Resolution

    To work around  this error, remove the Clock Control Blocks(ALTCLKCTRL) from the design and fit the design automatically.

    This problem is scheduled to be fixed ina future release of the Intel® Quartus® Prime Standard Edition software.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs

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