Article ID: 000080457 Content Type: Troubleshooting Last Reviewed: 05/20/2025

Why does my Estimated Delay Added for Hold Timing report include a false path?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Quartus® Prime Standard Edition
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Description

The Estimated Delay Added for Hold Timing report may include a false path because the fitter report is purely netlist-driven. It can't differentiate between multiple timing paths on the same connection. If a hold time critical path shares a common section with the path that has been set as a false path, both paths are considered delay-added paths by the fitter. The top 100 paths will show up in the report.

 

 

Resolution

It is safe to ignore the false paths in the Estimated Delay Added for Hold Timing Details section of the fitter report. 

Related Products

This article applies to 3 products

Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 GX FPGA

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