Article ID: 000080436 Content Type: Troubleshooting Last Reviewed: 07/03/2019

Why does AN830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design fails to perform auto-negotiation at 10Mbps and 100Mbps ?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Triple-Speed Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in AN830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design that was generated using Intel® Quartus® Prime Pro Edition version 17.1 software, Intel® FPGA Triple-Speed Ethernet IP core fails to perform auto-negotiation with link partner at 10Mbps and 100Mbps.

    This is because Intel® Stratix® 10 GX Signal Integrity Development Kit Board on-board Marvell* 88E1111 PHY chip is not configured to advertise 10Mbps and 100Mbps speed correctly during the auto-negotiation with the link partner. 

      

    Resolution

    To avoid this error, tse_marvel_phy.tcl script that's located in <project_directory>/sc_tcl of the reference design need to be amended with the following design changes.

     

    Include the following lines within the default { } condition at line 131 of the tse_marvel_phy.tcl script:

    if { $PHY_COPPER_DUPLEX == 1} {

        set quad_phy_register_value_temp [expr {$quad_phy_register_value_temp | 0x0140}];   

        puts "Advertise PHY 100BASE-TX & 10BASE-TX Full Duplex";

    } else {

        set quad_phy_register_value_temp [expr {$quad_phy_register_value_temp | 0x00A0}];

        puts "Advertise PHY 100BASE-TX & 10BASE-TX Half Duplex";

    }

     

    This problem is scheduled to be fixed in a future release of AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design. 

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