Why do I see Timing violations in the Intel® Stratix® V and Arria® V GZ devices when using the Intel® 50G and 100G Interlaken MegaCore® Function IP.

Due to a problem with the Intel® 50G and 100G Interlaken MegaCore® Function IP auto-generated sdc file, setup and recovery timing closure violations my be seen in 24 lane configurations with data rate 6.25G in the Intel® Quartus® Prime Standard versions 18.1.1 and earlier.

To work around this problem, when using the Intel® Quartus® Prime Standard versions 18.1.1 and earlier, replace the auto-generated ilk_core.sdc file with the version attached below.

ilk_core.sdc

This problem has been fixed starting with the Intel® Quartus® Prime Standard version 19.1