Article ID: 000080383 Content Type: Troubleshooting Last Reviewed: 02/08/2023

Why do I get a Fatal Error in Assembler when having ALTLVDS TX with a design?

Environment

    Intel® Quartus® Prime Standard Edition
    LVDS SERDES Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see this error in the Quartus® Prime Software Standard version 17.0 or earlier. This error is due to either LVDS data output port “tx_out[*]” or external clock port “tx_outclock” of ALTLVDS TX IP is not assigned to LVDS I/O standard.

 

 

Resolution

To work around this problem, you should assign both the data output port and external clock output to the LVDS I/O standard.

 

Related Products

This article applies to 9 products

Intel® Cyclone®
Arria® GX FPGA
Arria® II FPGAs
Arria® V FPGAs and SoC FPGAs
Stratix® FPGAs
Stratix® II FPGAs
Stratix® III FPGAs
Stratix® IV FPGAs
Stratix® V FPGAs

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