Article ID: 000080363 Content Type: Troubleshooting Last Reviewed: 12/31/2022

Why does Mentor* ModelSim* simulation of the eSRAM Intel® FPGA IP generate X in the waveform?

Environment

  • Intel® Quartus® Prime Pro Edition
  • eSRAM Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In the Modelsim* SE 2020 version software, you may see 'X' in the simulation of the eSRAM Intel® FPGA IP due to an encrypted code problem in the simulator.

    Resolution

    To work around this problem, run the simulation with the prior Modelsim* SE 2020 (e.g., Modelsim SE 2019.2) version. 

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.

     

     

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.