Article ID: 000080358 Content Type: Troubleshooting Last Reviewed: 12/15/2022

Why does the power-up trigger in the Signal Tap acquisition fail for Intel® Stratix® 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Starting in the Intel® Quartus® Prime Pro Edition Software version 19.1, you can use the nINIT_DONE signal generated from Reset Release Intel® Stratix® 10 FPGA IP to hold a control circuit in reset until the device has fully entered user mode.

    The nINIT_DONE signal can be used as the trigger condition in the Signal Tap power-up trigger to capture events that occur during device initialization. However, Intel® Quartus® Prime Pro Edition Software may randomly place the Signal Tap registers on either ALM or Hyper registers. When Hyper registers are used, the Signal Tap registers may not be able to reset to the correct state, which will not enable the power-up trigger.  

    Resolution

    To work around this problem, place all the Signal Tap registers in ALM registers using the following QSF (Quartus Settings File) assignment:

    set_instance_assignment -name REGISTER_LOCATION_TYPE ALM_REGISTER -to auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_auto_signaltap_0|sld_signaltap_inst -entity <project_top>

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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