Article ID: 000080329 Content Type: Error Messages Last Reviewed: 11/07/2014

Error (21180): Can't find the legal settings for PLL node "interlaken_inst|sv_pma:inst_sv_pma|sv_rx_pma:rx_pma.sv_rx_pma_inst|rx_pmas[0].rx_pma.rx_cdr" with reference clock frequency "500.0 MHz" and output clock frequency "6250.000004 MHz"

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug in the Quartus® II software version 14.0, you may see the Fitter error above when compiling the Seriallite III IP for Stratix® V devices using a datarate of 12.5Gbps and a transceiver reference clock frequency of 500MHz.

    Resolution

    You can extract the following parameters from the 13.1.4 Seriallite III IP top level RTL file and then transfer them to the 14.0 Seriallite III IP version.
                                                                           
    reference_clock_frequency => "312.500000 MHz",                                                
    pll_ref_freq       => "500.0 MHz",                                             
    data_rate         => "12500.000000 Mbps"                 

    Other datarates and transceiver REFCLK frequencies combinations for the Seriallite III IP may also produce the Fitter error above.  The same workaround can be applied by extracting the parameters from the 13.1.4 version and transferring them to 14.0 Seriallite III IP version.                                                                                             
                                                                           
    This is scheduled to be fixed in a future version of the Quartus II software. 

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA

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