Article ID: 000080306 Content Type: Troubleshooting Last Reviewed: 02/01/2016

Why does the Quartus Prime Pin Planner show a transceiver dedicated reference clock pin on the right side of an Arria 10 device that only has transceiver channels on the left side?

Environment

  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Arria® 10 devices that support transceiver channels on the left side only may have a dedicated transceiver REFCLK pin on the right hand side of the device. These pins do not connect to left-side transceivers, but you may use this to drive right-side fPLLs and core logic.

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