Why do I see a low restricted fmax when using a floating-point accumulator in Arria 10 DSP block?

This problem affects designs targeting Arria 10 DSP blocks’ floating-point mode and where you configure a DSP block to operate in a multiply-accumulate mode. You may see this problem if your design uses the ALTERA_FP_ACC_CUSTOMER IP core. The specification expected fMAX when fully pipelined exceeds 400 MHz. In the Quartus II software 15.0, the actual restricted fMAX is ~298MHz.

When using the DSP block multiply accumulate mode, use DSPBA tool to generate a circuit that takes advantage of it in DSP Builder advanced blockset.