Article ID: 000079954 Content Type: Error Messages Last Reviewed: 04/15/2015

Error (12857): HIP reset pin "perst" is locked to "PIN_&ltyour_PERST_ pin location&gt", which is not legal.

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in Quartus® II software version 13.1, you will see this error if you incorrectly hook up the DDR3 pins or have unconnected pins in the DDR portion of the device.  If you have such incorrect DDR pin connections you will see this error even if your PERST is on a legal and correct pin location.
    Resolution

    Correct the DDR pin errors.

    This problem is fixed in Quartus II software version 14.0.

    Related Products

    This article applies to 3 products

    Stratix® V GX FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA

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