- # ERROR: <path>/220model.vhd(741): Subprogram ">" is ambiguous. Suitable definitions exist in package 'std_logic_1164' and 'std_logic_signed'.
- # ERROR: <path>/220model.vhd(741): (Use the '-explicit' option to disable the previous error check)
- # ERROR: <path>/220model.vhd(748): Subprogram "=" is ambiguous. Suitable definitions exist in package 'std_logic_1164' and 'std_logic_signed'.
- # ERROR: <path>/220model.vhd(748): (Use the '-explicit' option to disable the previous error check)
- # ERROR: <path>/220model.vhd(793): VHDL Compiler exiting
Components such as LPM_COMPARE (signed and unsigned) use >, <, and = operators and also include the std_logic_1164 and std_logic_unsigned or std_logic_signed packages. These operators are overloaded; i.e., definitions for these operators are available in both packages, implicitly in std_logic_1164 and explicitly in std_logic_unsigned and signed.
By including the std_logic_unsigned or signed package along with std_logic_1164, the designer intends to use the explicit definition in the package rather than the implicit definition.
The 220model.vhd file contains many such operators and includes signed and unsigned packages for different components. When compiling this file in Modelsim, an explicit option must be specified to force the simulator to infer the explicit definition.
ModelSim > vcom 220model.vhd -explicit
Editing the ModelSim.ini file and setting the variable EXPLICIT = 1 sets this option as the default option for all compilations.