Description
The sampling rate for the SignalTap II logic analyzer is the frequency of the acquisition clock specified as Clock in the Signal Configuration panel in the SignalTap File (.stp).
Refer to the Timing Analysis section of the Compilation Report to find the maximum frequency of the logic analyzer clock.
For more information, refer to the Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in Volume 3 of the Quartus II handbook.