Article ID: 000079812 Content Type: Troubleshooting Last Reviewed: 11/18/2011

Reset Synchronizer for UniPHY External Memory Interfaces May Cause Design to Fail Timing when generated in SOPC Builder or Qsys

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

Systems generated with SOPC Builder or Qsys may fail timing closure due to paths that include a reset synchronizer.

Resolution

A workaround for this issue is to apply the following constraint in the TimeQuest Timing Analyzer:For SOPC Builder:

set_false_path -from {dut_sopc_top_reset_clk_0_domain_synch_module: dut_sopc_top_reset_clk_0_domain_synch*}

For Qsys:

set_false_path -from *:rst_controller*|*:alt_rst_sync_uq1| altera_reset_synchronizer_int_chain[*] -to *:controller_phy_inst| *:memphy_top_inst|*:umemphy|*:ureset|*:ureset_*_clk|reset_reg[*].

Related Products

This article applies to 1 products

Intel® Programmable Devices

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