Article ID: 000079522 Content Type: Troubleshooting Last Reviewed: 08/29/2012

Why does simulation show hold time violations for the Stratix_II_LVDS receiver primitive?


  • Simulation

    You may have this problem due to a known issue with the Standard Delay Format Output File (.sdo) timing file for the Stratix® II LVDS receiver primitive. Hold time violations appear between the data input and the clock signal for the dataout_reg instances of the bit_slip module.

    The Quartus® II timing analyzer does not report these hold time violations. The timing analyzer checks the receiver skew margin (RSKM) in the LVDS block and reports any violations. As long as the RSKM is satisfied, the hardware is guaranteed to work. The bit_slip circuit sets the final output bit correctly.

    Therefore, these hold violations from simulation of the LVDS receiver can be safely ignored.

    This issue is fixed in the Quartus II software version 5.0 SP1. Beginning with this software version, the SDO file does not include the hold time checks for the hardware that is guaranteed to work as long as the RSKM is met.

    Related Products

    This article applies to 1 products

    Stratix® II FPGAs



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