Description
This has to do with the readyLatency differences between the two modules. The Video IP (VIP) Suite Megacores® have a readyLatency = 1. The SC FIFO's default readyLatency = 0. Qsys flags this incompatibility with an error when trying to generate the system. Starting in Quartus® II software version 13.0 Qsys will automatically insert adapters to accommodate many incompatibilities, but in the case of the VIP Suite these adapters are intentionally not inserted.
Resolution
The readyLatency of the SC FIFO will need to be changed to "1" to match that of the VIP suite. You will need to edit the altera_avalon_sc_fifo_hw.tcl file found in your Quartus II software libraries. The path to this file is <quartus installation path>/<version>/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/. In this altera_avalon_sc_fifo_hw.tcl file change the appropriate "readyLatency" values to "1". Depending on your design, this may include changing the readyLatency of the Avalon-ST sink interface, source interface, and/or almost_full and almost_empty interfaces.