Article ID: 000079408 Content Type: Error Messages Last Reviewed: 09/11/2012

Error (10170): Verilog HDL Syntax Error at <filename> near text "int"; expecting an identifier ("int" is a reserved keyword)

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

In the Quartus® II software may generate this error when you declare multiple loop variables within a SystemVerilog FOR loop, because this syntax is currently unsupported.

The following is an example of unsupported syntax:
for(int i=0, int j=0; i<4, j<2; i , j )

To work around this problem, declare only one loop variable within the FOR loop.

Use the following supported syntax to work around this problem:
int j=0;
for(int i=0, j=0; i<4, j<2; i , j )

This problem is scheduled to be fixed in a future release of the Quartus II software.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1