Article ID: 000079309 Content Type: Troubleshooting Last Reviewed: 08/15/2023

Why do I see bit errors with my DDR3 controller?

Environment

    Quartus® II Subscription Edition
    DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
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Description

You may see bit errors with your DDR3 UniPHY memory controller if the REFRESH command period, tRFC, is set too low. 

Resolution

The memory controller could perform READ or WRITE commands before the REFRESH cycle has completed causing the corruption of data. Make sure to set the tRFC timing parameter in the Megawizard GUI to the correct value specified in the memory device datasheet.

Related Products

This article applies to 19 products

Stratix® IV E FPGA
Stratix® III FPGAs
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Arria® V GX FPGA
Cyclone® V GT FPGA
Arria® V GT FPGA
Arria® V GZ FPGA
Cyclone® V E FPGA
Cyclone® V GX FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA

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