Article ID: 000079123 Content Type: Product Information & Documentation Last Reviewed: 05/05/2015

How to deal with interface timing of EMAC RGMII on HPS part of SoC Device?


Description In Cyclone® V or Arria® V SoC FPGA, the RGMII transmit timing parameter Td (TX_CLK to TXD/TX_CTL output data delay) is specified as -0.85 to 0.15 ns, which exceeds the industry standard's specification. In Reduced Gigabit Media Independent Interface specification (version 2.0), the TskewT (data to clock output skew) with same definition to Td is defined as -500ps to 500ps. This timing violation will lead to interconnection problem between HPS EMAC RGMII interface and some vendor's PHY.
Resolution We recommend to select the PHY with ability to adjust its input timing. For example, selecting Realtek\'s RTL8212 serial PHY, it provides TXDLY / RXDLY pins to adjust its input / output clock delay; selecting Micrel\'s KSZ9021 serial PHY, it provides RGMII Pad Skew registers  to adjust the signals\' skew in step of 0.12ns. Both of those means add addtional delay to signals to compensate the output skew, which can eliminate the timing error in customer board.
For selecting those PHYs without ability to adjust timing, additional glue logic should be applied to the RGMII interface, routing the external HPS EMAC RGMII signals to FPGA side, or bridging HPS EMAC GMII internally to FPGA.

Related Products

This article applies to 5 products

Arria® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Arria® V SX SoC FPGA